// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
/*
 * Copyright (C) 2022 rengaomin@allwinnertech.com
 */

#ifndef _DT_BINDINGS_CLK_SUN55IW3_H_
#define _DT_BINDINGS_CLK_SUN55IW3_H_

#define CLK_PLL_DDR		0
#define CLK_PLL_PERI0_PARENT	1
#define CLK_PLL_PERI0_2X	2
#define CLK_PERI0_DIV3		3
#define CLK_PLL_PERI0_800M	4
#define CLK_PLL_PERI0_480M	5
#define CLK_PLL_PERI0_600M	6
#define CLK_PLL_PERI0_400M	7
#define CLK_PLL_PERI0_300M	8
#define CLK_PLL_PERI0_200M	9
#define CLK_PLL_PERI0_160M	10
#define CLK_PLL_PERI0_16M	11
#define CLK_PLL_PERI0_150M	12
#define CLK_PLL_PERI0_25M	13
#define CLK_PLL_PERI1_PARENT	14
#define CLK_PLL_PERI1_2X	15
#define CLK_PLL_PERI1_800M	16
#define CLK_PLL_PERI1_480M	17
#define CLK_PLL_PERI1_600M	18
#define CLK_PLL_PERI1_400M	19
#define CLK_PLL_PERI1_300M	20
#define CLK_PLL_PERI1_200M	21
#define CLK_PLL_PERI1_160M	22
#define CLK_PLL_PERI1_150M	23
#define CLK_PLL_GPU		24
#define CLK_PLL_VIDEO0_PARENT	25
#define CLK_PLL_VIDEO0_4X	26
#define CLK_PLL_VIDEO0_3X	27
#define CLK_PLL_VIDEO1_PARENT	28
#define CLK_PLL_VIDEO1_4X	29
#define CLK_PLL_VIDEO1_3X	30
#define CLK_PLL_VIDEO2_PARENT	31
#define CLK_PLL_VIDEO2_4X	32
#define CLK_PLL_VIDEO2_3X	33
#define CLK_PLL_VIDEO3_PARENT	34
#define CLK_PLL_VIDEO3_4X	35
#define CLK_PLL_VIDEO3_3X	36
#define CLK_PLL_VE		37
#define CLK_PLL_AUDIO0_4X	38
#define CLK_PLL_AUDIO0_2X	39
#define CLK_PLL_AUDIO0_1X	40
#define CLK_PLL_AUDIO0_DIV_48M	41
#define CLK_PLL_NPU_4X		42
#define CLK_PLL_NPU_2X		43
#define CLK_PLL_NPU_1X		44
#define CLK_TRACE		45
#define CLK_AHB			46
#define CLK_APB0		47
#define CLK_APB1		48
#define CLK_MBUS		49
#define CLK_NSI			50
#define CLK_GIC			51
#define CLK_DE			52
#define CLK_DE0			53
#define CLK_DI			54
#define CLK_BUS_DI		55
#define CLK_G2D			56
#define CLK_BUS_G2D		57
#define CLK_GPU			58
#define CLK_BUS_GPU		59
#define CLK_CE			60
#define CLK_CE_SYS		61
#define CLK_BUS_CE		62
#define CLK_VE			63
#define CLK_BUS_VE		64
#define CLK_NPU			65
#define CLK_DMA			66
#define CLK_MSGBOX0		67
#define CLK_SPINLOCK		68
#define CLK_TIMER		69
#define CLK_DBGSYS		70
#define CLK_PWM1		71
#define CLK_PWM			72
#define CLK_IOMMU		73
#define CLK_BUS_IOMMU		74
#define CLK_TIMER0		75
#define CLK_TIMER1		76
#define CLK_TIMER2		77
#define CLK_TIMER3		78
#define CLK_TIMER4		79
#define CLK_TIMER5		80
#define CLK_DRAM		81
#define CLK_GMAC1_MBUS_GATE	82
#define CLK_ISP_MBUS_GATE	83
#define CLK_CSI_MBUS_GATE	84
#define CLK_USB3_MBUS_GATE	85
#define CLK_NAND_MBUS_GATE	86
#define CLK_CE_MBUS_GATE	87
#define CLK_VE_MBUS_GATE	88
#define CLK_DMA_MBUS_GATE	89
#define CLK_BUS_DRAM		90
#define CLK_NAND0		91
#define CLK_NAND0_CLK0		92
#define CLK_NAND0_CLK1		93
#define CLK_SMHC0		94
#define CLK_SMHC1		95
#define CLK_SMHC2		96
#define CLK_BUS_SMHC2		97
#define CLK_BUS_SMHC1		98
#define CLK_BUS_SMHC0		99
#define CLK_SYSDAP		100
#define CLK_UART7		101
#define CLK_UART6		102
#define CLK_UART5		103
#define CLK_UART4		104
#define CLK_UART3		105
#define CLK_UART2		106
#define CLK_BUS_UART1		107
#define CLK_BUS_UART0		108
#define CLK_TWI5		109
#define CLK_TWI4		110
#define CLK_TWI3		111
#define CLK_TWI2		112
#define CLK_TWI1		113
#define CLK_TWI0		114
#define CLK_SPI0		115
#define CLK_SPI1		116
#define CLK_SPI2		117
#define CLK_SPIF		118
#define CLK_BUS_SPIF		119
#define CLK_BUS_SPI2		120
#define CLK_BUS_SPI1		121
#define CLK_BUS_SPI0		122
#define CLK_GMAC0_25M		123
#define CLK_GMAC1_25M		124
#define CLK_GMAC1		125
#define CLK_GMAC0		126
#define CLK_IRRX		127
#define CLK_BUS_IRRX		128
#define CLK_IRTX		129
#define CLK_BUS_IRTX		130
#define CLK_GPADC0_24M		131
#define CLK_GPADC1_24M		132
#define CLK_BUS_GPADC0		133
#define CLK_BUS_GPADC1		134
#define CLK_THS			135
#define CLK_DCXO12M		136
#define CLK_USB0		137
#define CLK_USB1		138
#define CLK_USB2_REF		139
#define CLK_USB3_REF		140
#define CLK_USB3_SUSPEND	141
#define CLK_USBOTG0		142
#define CLK_USBEHCI1		143
#define CLK_USBEHCI0		144
#define CLK_USBOHCI1		145
#define CLK_USBOHCI0		146
#define CLK_LRADC		147
#define CLK_PCIE_AUX		148
#define CLK_DPSS_TOP0		149
#define CLK_DPSS_TOP1		150
#define CLK_HDMI_24M		151
#define CLK_HDMI_CEC		152
#define CLK_HDMI		153
#define CLK_DSI0		154
#define CLK_DSI1		155
#define CLK_BUS_DSI1		156
#define CLK_BUS_DSI0		157
#define CLK_VO0_TCONLCD0	158
#define CLK_VO0_TCONLCD1	159
#define CLK_VO1_TCONLCD0	160
#define CLK_COMBPHY0		161
#define CLK_COMBPHY1		162
#define CLK_BUS_VO1_TCONLCD0	163
#define CLK_BUS_VO0_TCONLCD1	164
#define CLK_BUS_VO0_TCONLCD0	165
#define CLK_TCONTV		166
#define CLK_TCONTV1		167
#define CLK_BUS_TCONTV1		168
#define CLK_BUS_TCONTV		169
#define CLK_EDP			170
#define CLK_BUS_EDP		171
#define CLK_LEDC		172
#define CLK_BUS_LEDC		173
#define CLK_CSI			174
#define CLK_CSI_MASTER0		175
#define CLK_CSI_MASTER1		176
#define CLK_CSI_MASTER2		177
#define CLK_CSI_MASTER3		178
#define CLK_BUS_CSI		179
#define CLK_ISP			180
#define CLK_DSP			181
#define CLK_CPUS_HCLK_GATE	182
#define CLK_USB_24M		183
#define CLK_FANOUT_50M		184
#define CLK_FANOUT_25M		185
#define CLK_FANOUT_16M		186
#define CLK_FANOUT_12M		187
#define CLK_FANOUT_24M		188
#define CLK_CLK27M_FANOUT	189
#define CLK_CLK_FANOUT		190
#define CLK_FANOUT2		191
#define CLK_FANOUT1		192
#define CLK_FANOUT0		193

#define CLK_MAX_NO		(CLK_FANOUT0 + 1)

#endif /* _DT_BINDINGS_CLK_SUN55IW3_H_ */
